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Verilog Write File

Submitted by abettino on Wed, 06/02/2010 - 14:42

It is often desired to write data out to a file during a Verilog simulation. Fortunately, Verilog provides a simple way to do this. It is very similar to the way file writing is accomplished in C.

module verilog_write_file;
   integer file,ii;
   initial begin
      file = $fopen("test_output.dat");
      for (ii=0;ii<256;ii=ii+1) begin
         $fwrite(file,"%x\n",ii);
      end
      $stop;
   end
endmodule

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