Verilog monitor

The $monitor system task in Verilog can be used to display a state of a signal every time it changes. The following snippets demonstrates how the $monitor system task can be used to display the values of a and b as the simulation progresses.

module monitor_test;
 
reg [7:0] a, b;
 
initial begin
  $monitor("a=%d b=%d",a,b);
  #10 a = 0;
  b = 4;
  #100 a = 22;
  #100 b = 100;
  #100 a = 35;
  #100 b = 0;
  #10 $stop;
end
 
endmodule