Generate Statement
Submitted by abettino on Wed, 02/24/2010 - 20:10
Generate statements in Verilog provide a convenient means for instantiating the same module multiple times. The snippet below shows a simple example where a flip flop is instantiated a parameterized number of times.
module generate_module #(parameter NUM_INSTS = 3) ( input clk, // clock signal. input [NUM_INSTS-1:0] d, // data input. output [NUM_INSTS-1:0] q // data output. ); genvar ii; // variable used for generate loop. generate for(ii=0;ii<NUM_INSTS;ii=ii+1) begin : INST_GEN rising_edge_ff rising_edge_ff ( .clk (clk ), .d (d[ii]), .q (q[ii]) ); end endgenerate endmodule // generic flip flop. module rising_edge_ff ( input clk, // clock signal. input d, // data input. output reg q // data output ); always @(posedge clk) begin q <= d; end endmodule
| Attachment | Size |
|---|---|
| generate.v | 743 bytes |
bug?
wouldn't this read d[ii] and q[ii] instead of d[i] and q[i]?
Yes you are correct. It has
Yes you are correct. It has been updated. Thanks!