Verilog For Loop

The Verilog for loop is very similar to the for loop in C. The block is created with the begin and end keywords just like other blocks in Verilog. Notice that the ++ operator is not supported for incrementing variables in Verilog 2001, but it is supported in SystemVerilog.

module verilog_for;
integer ii;
initial begin
  for(ii=0;ii<10;ii=ii+1) begin
    $display("ii=%d",ii);
  end
  $stop;
end
endmodule;