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Verilog Carry Look Ahead Adder

Submitted by abettino on Mon, 04/05/2010 - 15:37

The carry look ahead adder is similar to the Ripple Carry Adder, but it can operate faster due to the way that the carry logic is generated. For more information about the algorithm, see the Wikipedia page. This snippet is a parametrizable implementation of the carry look ahead adder.

module cla #(parameter WIDTH=4)
(
   input      [WIDTH-1:0] a,b
   output reg [WIDTH:0]   sum
);
reg [WIDTH:0]             carry;
reg [WIDTH-1:0]           g,p;
integer                   ii;
 
always @* begin
  carry[0]      = 1'b0;
  for(ii=0;ii<WIDTH;ii=ii+1) begin
    g[ii]       = a[ii] & b[ii];
    p[ii]       = a[ii] ^ b[ii];
    carry[ii+1] = g[ii] | (p[ii] & carry[ii]);
    sum[ii]     = p[ii] ^ carry[ii];
  end
  sum[WIDTH]    = carry[WIDTH];
end
endmodule

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