Verilog Always

The always block in verilog can be used to model either combinational or sequential logic. It starts with the always keyword and then the sensitivity list. After that is the begin and end along with an optional block label.

 
always @(posedge clk or negedge n_reset)
  begin : FLIP_FLOP
    if (!n_reset) begin
      q <= 1'b0;
    end
    else begin
      q <= d;
    end
  end