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Verilog Task

Submitted by abettino on Thu, 04/01/2010 - 13:34

The task in Verilog provides a convenient mechanism for encapsulating a chunk of code that will be executed multiple times. The most useful place for a task is in a testbench. The following snippets demonstrates the syntax for the task in verilog. Notice that first comes the task name followed by the inputs and outputs for the task. The initial block shows how the task can be called.

module verilog_task;
 
task add;
input [7:0] a;
input [7:0] b;
output [7:0] c;
  begin
    c = a + b;
  end
endtask
 
integer value1, value2,value3;
 
initial begin
  for(value1=0;value1<10;value1=value1+1) begin
    for(value2=0;value2<10;value2=value2+1) begin
      add(value1,value2,value3);
      $display("value1 = %d value2 = %d value3 = %d",value1,value2,value3);
      if (value3 != (value1 + value2)) $display("ERROR");
    end
  end
  $stop;
end
 
endmodule

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