Skip navigation.
Home
hdlsnippets
Verilog Snippets | VHDL Snippets | SystemVerilog Snippets | About | Links
Home

SystemVerilog Dynamic Array

Submitted by abettino on Mon, 03/29/2010 - 12:52

Dynamic arrays in SystemVerilog allow for the creation of arrays during simulation runtime. It is no longer necessary to know the size of the array before the simulation starts executing. This snippet demonstrates how to create a dynamic array and how to add more elements to the array during runtime. The second array in the example also shows how it may be possible to inadvertently erase an entire array while attempting to allocate more items in the array.

module systemverilog_dynamic_array;
int test_array[];  // dynamic array syntax.
 
initial begin
  test_array = new[20];      // allocate 20 items in this array.
  foreach (test_array[ii])
    test_array[ii] = ii;     // put the value ii in the iith position
  $display("First array");
  foreach (test_array[ii])
    $display("test_array[%d] = %d",ii,test_array[ii]);
 
  test_array = new[50];       // allocate 50 items now. This erases the first array.
  $display("Second array");
  foreach (test_array[ii])
    $display("test_array[%d] = %d",ii,test_array[ii]);
  foreach (test_array[ii])
    test_array[ii] = ii;
 
  test_array = new[60](test_array);  // allocate 10 additional items into the array.
  $display("Third array");    
  foreach (test_array[ii])
    $display("test_array[%d] = %d",ii,test_array[ii]);
 
  $stop;
end
endmodule

»