module verilog_tb;

reg  clk;              // clk signal.
reg  reset;            // reset signal.
reg  input_a, input_b; // input signals.
wire output_a;         // output signal.

// The unit under test.
test_module uut 
(
  .clk      (clk),
  .reset    (reset),
  .input_a  (input_a),
  .input_b  (input_b),
  .output_a (output_a)
);

// clock generation.
initial begin
  clk <= 1'b0;
  forever #10 clk = ~clk;
end

// main stimulus.
initial begin
  reset = 1'b1;
  input_a = 0;
  input_b = 0;
  repeat (100) @(posedge clk);
  reset = 1'b0;
  @(posedge clk);
  input_a = 1;
  input_b = 0;
  @(posedge clk);
  input_a = 1;
  input_b = 1;
  @(posedge clk);
  input_a = 0;
  input_b = 0;
  @(posedge clk);
  input_a = 0;
  input_b = 1;
  repeat (10) @(posedge clk);
  $stop;
end

endmodule


// simple test module for test bench.
module test_module
(
 input      clk,
 input      reset,
 input      input_a,
 input      input_b,
 output reg output_a
);


always @(posedge clk)
  if (reset) output_a <= 1'b0;
  else       output_a <= input_a | input_b;

endmodule