module verilog_sm
(
   input         clk,
   input         reset,
   input         enable,
   output  [1:0] system_out
 );

// State encodings.
parameter [1:0]   STATE_0 = 2'b00,
                  STATE_1 = 2'b01,
                  STATE_2 = 2'b10,
                  STATE_3 = 2'b11;

reg [1:0]         current_state, next_state;

// Current state register.
always @(posedge clk or posedge reset)
  if (reset) current_state <= STATE_0;
  else       current_state <= next_state;

// Next State logic.
always @* begin
  next_state = 'bx;
  case (current_state)
    STATE_0 : if (enable)  next_state = STATE_1;
              else         next_state = STATE_0;
    STATE_1 :              next_state = STATE_2;
    STATE_2 :              next_state = STATE_3;
    STATE_3 : if (!enable) next_state = STATE_0;
              else         next_state = STATE_3;
  endcase
end

// Output control logic.
always @(posedge clk) begin
  case (current_state)
    STATE_0 : system_out <= 2'b00;
    STATE_1 : system_out <= 2'b01;
    STATE_2 : system_out <= 2'b10;
    STATE_3 : system_out <= 2'b11;
  endcase
end

endmodule