module verilog_ram_infr #(parameter ADDR_WIDTH=8, DATA_WIDTH=8, DEPTH=256)
(
 input                   clk,       // clock signal.
 input  [ADDR_WIDTH-1:0] addr,      // address signal.
 input                   we,        // write enable signal.
 input  [DATA_WIDTH-1:0] data_in,   // data input.
 output [DATA_WIDTH-1:0] data_out   // data output.
);

reg [DATA_WIDTH-1:0]     mem [0:DEPTH-1]; // memory array.

always @(posedge clk)
  if (we) mem[addr] <= data_in;       // latch data on we.

assign data_out = mem[addr];          // data output.

endmodule

module tbverilog_ram;
reg        clk,we;
reg  [7:0] addr,data_in;
wire [7:0] data_out;

initial begin
  clk = 1'b0;
  forever #10 clk = ~clk;
end

verilog_ram_infr dut
  (
   .clk     (clk     ),
   .addr    (addr    ),
   .we      (we      ),
   .data_in (data_in ),
   .data_out(data_out)
   );

integer ii;
initial begin
  for (ii=0;ii<256;ii=ii+1) begin
    @(posedge clk);
    data_in = ii;
    addr = ii;
    we = 1;
  end

  @(posedge clk);
  we = 0;

  for (ii=0;ii<256;ii=ii+1) begin
    addr = ii;
    @(posedge clk);
    if (data_out != ii) $display("error data_out=%d ii=%d",data_out,ii);
  end
  $stop;
end

endmodule