`define USE_MODULE_A 

module verilog_if_def_example
(
   input      clk,
   input      din,
   output reg dout
);

// instantiate either Module A or B 
// depending on the `ifdef
`ifdef USE_MODULE_A
module_a module_inst
(
  .clk (clk),
  .din (din),
  .dout(dout)
);
`else
module_b module_inst
(
  .clk (clk),
  .din (din),
  .dout(dout)
);
`endif

endmodule

// simple positive edge flip flop
module module_a
(
   input      clk,
   input      din,
   output reg dout
);

always @(posedge clk) 
  dout <= din;

endmodule

// simple negative edge flip flop
module module_b
(
   input      clk,
   input      din,
   output reg dout
);

always @(negedge clk) 
  dout <= din;

endmodule