module tb_system_verilog_sm;


bit clk;
bit reset;
bit enable;

logic [1:0] system_out;

always #10 clk = ~clk;

system_verilog_sm dut
(
 .clk(clk),
 .reset(reset),
 .enable(enable),
 .system_out(system_out)
 );


initial begin
  enable = 0;
  repeat (10) @(posedge clk);
  enable = 1;
  repeat (10) @(posedge clk);
  enable = 0;
  repeat (10) @(posedge clk);
  $stop;
end
    

endmodule