module serial_in_parallel_out #(parameter WIDTH=8) (
  input  clk,
  input  data_in,                     
  output [WIDTH-1:0] data_out
                     );

// register to hold shift values.
reg [WIDTH-1:0] shift_reg;

// sync process.
always @(posedge clk)
  shift_reg <= {data_in,shift_reg[WIDTH-1:1]};

// data output of shift register.
assign data_out = shift_reg;

endmodule