module  parameterized_module #(parameter DWIDTH=8, AWIDTH=10)
(
  input               clk,
  input  [DWIDTH-1:0] data_in,
  input  [AWIDTH-1:0] address,
  input               write_enable,
  output [DWIDTH-1:0] data_out
);

parameter [AWIDTH-1:0] DESIRED_ADDRESS = 0;

reg [DWIDTH-1:0]      data_reg;

always @(posedge clk) begin
  if (write_enable && address == DESIRED_ADDRESS) data_reg <= data_in;
end

assign data_out = data_reg;

endmodule

module instantiate_parameterized_module;

reg         clk;
reg  [31:0] data_in;
reg  [31:0] address;
reg         write_enable;
wire [31:0] data_out;

parameterized_module #(.DWIDTH(32),.AWDITH(32)) parameterized_module_inst
(
 .clk         (clk         ),
 .data_in     (data_in     ),
 .address     (address     ),
 .write_enable(write_enable),
 .data_out    (data_out    )
);

endmodule