// Odd clock divider. Supported input div_factors
// are 3,5,7, and 9.
module odd_divide
(
 input          clk,        // clock to divide.
 input          reset,      // reset.
 input    [3:0] div_factor, // 3,5,7 or 9
 output         clk_div     // divided clock
);

reg 	   clk_neg,clk_pos;
reg  [3:0] div_counter;
wire [3:0] thresh = div_factor - 1;

// Divide counter.
always @(posedge clk or posedge reset) 
  if      (reset)               div_counter <= 0;
  else if (div_counter==thresh) div_counter <= 0;
  else                          div_counter <= div_counter+1;

// Clock neg logic.
always @(negedge clk) begin
  case (div_factor)
    4'h3    : clk_neg <= div_counter[1];
    4'h5    : clk_neg <= div_counter[1];
    4'h7    : clk_neg <= div_counter[2];
    4'h9    : clk_neg <= div_counter[2];
    default : clk_neg <= div_counter[1];
  endcase
end

// Clock pos logic.
always @* begin
  case (div_factor)
    4'h3    : clk_pos = div_counter[1];
    4'h5    : clk_pos = div_counter[1];
    4'h7    : clk_pos = div_counter[2];
    4'h9    : clk_pos = div_counter[2];
    default : clk_pos = div_counter[1];
  endcase
end

// output clock.
assign clk_div = clk_pos | clk_neg;

endmodule