module mux4_2
(
 input       a,
 input       b,
 input       c,
 input       d,
 input [1:0] sel,
 output reg  z
);

always @* begin
  case (sel)
    2'b00 : z = a;
    2'b01 : z = b;
    2'b10 : z = c;
    2'b11 : z = d;
  endcase
end

endmodule


module mux4_2_incomplete
(
 input       a,
 input       b,
 input       c,
 input [1:0] sel,
 output reg  z
);

always @* begin
  case (sel)
    2'b00   : z = a;
    2'b01   : z = b;
    2'b10   : z = c;
    default : z = 1'bx;
  endcase
end

endmodule

endmodule