module mux4_2
(
 input  logic       a,b,c,d,
 input  logic [1:0] sel,
 output logic       z
);

always_comb begin
  unique case (sel)
    2'b00 : z = a;
    2'b01 : z = b;
    2'b10 : z = c;
    2'b11 : z = d;
  endcase
end

endmodule


module mux4_2_incomplete
(
 input  logic       a,b,c,
 input  logic [1:0] sel,
 output logic       z
);

always_comb begin
  unique case (sel)
    2'b00   : z = a;
    2'b01   : z = b;
    2'b10   : z = c;
    default : z = 'x;
  endcase
end

endmodule