module generate_module #(parameter NUM_INSTS = 3)
(
  input                  clk,        // clock signal.
  input  [NUM_INSTS-1:0] d,          // data input.
  output [NUM_INSTS-1:0] q           // data output.
);

genvar 	     ii;                     // variable used for generate loop.

generate for(ii=0;ii<NUM_INSTS;ii=ii+1) begin : INST_GEN
rising_edge_ff rising_edge_ff (
			       .clk (clk ),
			       .d   (d[i]),  
			       .q   (q[i]) 
			       );
end
endgenerate
endmodule

// generic flip flop.
module rising_edge_ff (
  input      clk,        // clock signal.
  input      d,          // data input.
  output reg q           // data output
);

always @(posedge clk) begin
  q <= d;
end

endmodule