library ieee;
use ieee.std_logic_1164.all;

entity flip_flop_rising is
  port ( clk : in  std_logic;
         d   : in  std_logic;
         q   : out std_logic);
end flip_flop_rising;

architecture rtl of flip_flop_rising is
  begin
    process (clk)
    begin
      if (clk'event and clk='1') then
        q <= d;
      end if;
    end process;
  end rtl;


library ieee;
use ieee.std_logic_1164.all;

entity flip_flop_falling is
  port ( clk : in  std_logic;
         d   : in  std_logic;
         q   : out std_logic);
end flip_flop_falling;

architecture rtl of flip_flop_falling is
  begin
    process (clk)
    begin
      if (clk'event and clk='0') then
        q <= d;
      end if;
    end process;
  end rtl;



library ieee;
use ieee.std_logic_1164.all;

entity async_reset_ce is
  port ( clk     : in  std_logic;
         n_reset : in  std_logic;
         ce      : in  std_logic;
         d       : in  std_logic;
         q       : out std_logic);
end async_reset_ce;

architecture rtl of async_reset_ce is
  begin
    process (clk,n_reset)
    begin
      if (n_reset='0') then
        q <= '0';
      elsif (clk'event and clk='0') then
        if (ce = '1') then
          q <= d;
        end if;
      end if;
    end process;
  end rtl;