Parameterized Ripple Carry Adder
Submitted by abettino on Tue, 03/02/2010 - 21:40
A common task when one is learning Verilog is to create a Ripple Carry Adder out of a series of full adders. The obvious way to do this is to create a full adder module and then connect them together manually. A more elegant way to achieve the same result is with Verilog's generate statement.
Here is the basic full adder for reference:
module full_adder ( input a, input b, input cin, output sum, output cout ); assign sum = a ^ b ^ cin; assign cout = (a & b) | ((a^b) & cin); endmodule
And here is the parameterized ripple carry adder.
// Parameterized Ripple carry adder. module rca #(parameter N=4) ( input [N-1:0] A, input [N-1:0] B, output [N:0] sum ); // generate variable. genvar ii; wire [N:0] carry_out; // assing the first carry in bit to 0. assign carry_out[0] = 1'b0; // generate statement connect all the wires. generate for (ii=0;ii<N;ii=ii+1) begin : RCA_GEN full_adder full_adder ( .a(A[ii]), .b(B[ii]), .cin(carry_out[ii]), .cout(carry_out[ii+1]), .sum(sum[ii]) ); end endgenerate // assign the final sum bit. assign sum[N] = carry_out[N]; endmodule
| Attachment | Size |
|---|---|
| adder.v | 1.24 KB |