Generate Statement

Submitted by abettino on Wed, 02/24/2010 - 20:10

Generate statements in Verilog provide a convenient means for instantiating the same module multiple times. The snippet below shows a simple example where a flip flop is instantiated a parameterized number of times.

 
module generate_module #(parameter NUM_INSTS = 3)
(
  input                  clk,        // clock signal.
  input  [NUM_INSTS-1:0] d,          // data input.
  output [NUM_INSTS-1:0] q           // data output.
);
 
genvar 	     ii;                     // variable used for generate loop.
 
generate for(ii=0;ii<NUM_INSTS;ii=ii+1) begin : INST_GEN

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Multiplexer

Submitted by abettino on Wed, 02/24/2010 - 20:04

Multiplexers are easy to code in Verilog. Make sure that when describing combinational logic such as this to complete the case statements. If this is not done, unintentional latches may be inferred. Also notice the wildcard in the sensitivity list. This can be a very useful shortcut.

module mux4_2
(
 input       a,
 input       b,
 input       c,
 input       d,
 input [1:0] sel,
 output reg  z
);
 
always @* begin
  case (sel)
    2'b00 : z = a;
    2'b01 : z = b;
    2'b10 : z = c;
    2'b11 : z = d;
  endcase
end
 
endmodule

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Parameterized Priority Selector

Submitted by abettino on Wed, 02/03/2010 - 18:43

A parameterized priority selector can be written much more concisely than if each input encoding was explicitly coded. Also notice that with the SystemVerilog parameter syntax, we can use the parameter in the port list before it is actually declared.

module parameterized_priority
(
 input  logic [NUM_INPUTS-1:0] input_data,
 input  logic [NUM_INPUTS-1:0] select,
 output logic                  output_data
);
 
parameter NUM_INPUTS=5;
int                            ii;
 
always_comb begin
  output_data = 'x;

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VHDL Flip Flops

Submitted by abettino on Wed, 02/03/2010 - 08:09

This snippet demonstrates some basic flip flop styles in VHDL.

Rising edge triggered flip flop.

library ieee;
use ieee.std_logic_1164.all;
 
entity flip_flop_rising is
  port ( clk : in  std_logic;
         d   : in  std_logic;
         q   : out std_logic);
end flip_flop_rising;
 
architecture rtl of flip_flop_rising is
  begin
    process (clk)
    begin
      if (clk'event and clk='1') then
        q <= d;
      end if;
    end process;
  end rtl;

Falling edge triggered flip flop.

library ieee;

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Verilog 2001 Parameterized Module

Submitted by abettino on Tue, 02/02/2010 - 21:23

This snippet shows the syntax for creating a parameterized module with the Verilog 2001 style port list. This allows the signals in the port list to have parameterized widths.

The module is created with the parameter names after the module name.

module  parameterized_module #(parameter DWIDTH=8, AWIDTH=10)
(
  input               clk,
  input  [DWIDTH-1:0] data_in,
  input  [AWIDTH-1:0] address,
  input               write_enable,
  output [DWIDTH-1:0] data_out
);
 
parameter [AWIDTH-1:0] DESIRED_ADDRESS = 0;
 
reg [DWIDTH-1:0]      data_reg;

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Verilog Flip Flops

Submitted by abettino on Tue, 02/02/2010 - 08:17

Here are a few examples of flip flops. From these examples, one should be able to build any variation of the desired asynchronous set, resets and clears. These snippets use the Verilog 2001 style port listing.

Rising edge flip flop.

module rising_edge_ff (
  input      clk,        // clock signal.
  input      d,          // data input.
  output reg q           // data output
);
 
always @(posedge clk) begin
  q <= d;
end
 
endmodule

Falling edge flip flop.

module falling_edge_ff (

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