A register is a basic type in Verilog. It can be used to model both combinational and sequential logic. A verilog register must be assigned from within either an always or an initial block. The basic syntax is the reg keyword followed by the width of the signal and the name. Also see Verilog Flip Flops for the way to code flip flops in Verilog.

reg [7:0] example_reg;
 
always @* begin
  example_reg = foo;
end

This Verilog subtractor uses this Ripple Carry Adder in order to realize a subtracter. It is important to keep in mind that the inputs represent signed two's complement values. The first thing this snippet does take the two's complement of the B input value and then feed it into another RCA.
Subtractor.

// Performs the operation A-B
module sub_4bit
(
 input  [3:0] A,
 input  [3:0] B,
 output [3:0] diff
 );
 
wire [3:0]     B2Comp;
 
rca twocomp
(
 .A(~B),
 .B(4'b1),
 .sum(B2Comp)
 );
 
rca subtract
(
 .A(A),
 .B(B2Comp),

This snippet demonstrates a straight forward approach to implementing a 4 bit Ripple Carry Adder in Verilog. Also check out the parameterized approach which scales very well.

Basic full adder.

module full_adder
(
  input  a,
  input  b,
  input  cin,
  output sum,
  output cout
);
 
assign sum = a ^ b ^ cin;
assign cout = (a & b) | ((a^b) & cin);
 
endmodule

4 bit ripple carry adder.

// Ripple carry adder.
module rca 
(

A common task when one is learning Verilog is to create a Ripple Carry Adder out of a series of full adders. The obvious way to do this is to create a full adder module and then connect them together manually. A more elegant way to achieve the same result is with Verilog's generate statement.

Here is the basic full adder for reference:

module full_adder
(
  input  a,
  input  b,
  input  cin,
  output sum,
  output cout
);
 
assign sum = a ^ b ^ cin;

This snippet demonstrates a Verilog implementation of a parameterized priority encoder. Also see the SystemVerilog parameterized priority encoder.

module parameterized_priority_encoder #(parameter INPUT_WIDTH=8,OUTPUT_WIDTH=3)
(
 input      [INPUT_WIDTH-1:0]  input_data,
 output reg [OUTPUT_WIDTH-1:0] output_data
);
 
integer                            ii;
 
always @* begin
  output_data = {OUTPUT_WIDTH{1'bx}};
  for(ii=0;ii<INPUT_WIDTH;ii=ii+1) if (input_data[ii]) output_data = ii;
end
 
endmodule  

This SystemVerilog parameterizer priority encoder is very similar to the SystemVerilog Parameterized Selector.

module parameterized_priority_encoder #(parameter INPUT_WIDTH=8,OUTPUT_WIDTH=3)
(
 input  logic [INPUT_WIDTH-1:0]  input_data,
 output logic [OUTPUT_WIDTH-1:0] output_data
);
 
int                            ii;
 
always_comb begin
  output_data = 'x;
  for(ii=0;ii<INPUT_WIDTH;ii++) if (input_data[ii]) output_data = ii;
end
 
endmodule  

This is a simple Verilog counter with clear and enable signals. The width of the counter is configurable with the parameter.

module counter_clear #(parameter WIDTH=8) 
(
 input                  clk,
 input                  clear,
 input                  enable,
 output reg [WIDTH-1:0] count
);
 
always @(posedge clk)
  if      (clear)  count <= 0;
  else if (enable) count <= count + 1;
 
endmodule

There may be many situations where it is desired to divide an input clock by an odd value. This verilog module demonstrates how and odd clock divider can be constructed for divide values of 3,5,7 or 9. It can be expanded to support other divide factors as well.

// Odd clock divider. Supported input div_factors
// are 3,5,7, and 9.
module odd_divide
(
 input          clk,        // clock to divide.
 input          reset,      // reset.
 input    [3:0] div_factor, // 3,5,7 or 9
 output         clk_div     // divided clock
);
 
reg 	   clk_neg,clk_pos;

A Verilog state machine can be coded very clearly and concisely with separate always blocks for the next state combinational logic and the current state registers. It is also convenient to split other sequential logic, such as for output signals or other data processing, into a separate always block. This makes it easy to visually identify the state transitions and to modify the state machine without much hassle.

This state machine performs the same behaviour as the one described in the SystemVerilog section. Please see SystemVerilog State Machine.

SystemVerilog provides a few enhancements to Verilog 2001 that can be utilized when coding a state machine. The following example uses the always_ff, always_comb, and unique case keywords that can help reduce simulation and synthesis mismatches. Also the enum construct is used to create the state labels. This example state machine just outputs the state number that it is currently in. It waits to be enabled and will remain in the final state until disabled. A simple test bench is also provided for reference.

module system_verilog_sm
(
   input   logic       clk,