Often when connecting to an off chip component it is necessary to use a bidirectional signal for something like the data bus. This snippet demonstrates how this can be accomplished.

SystemVerilog introduced the interface as a means to abstract the connectivity between modules. At the most basic level, it can be used to group together wires that make up a bus in a design. This snippet demonstrates how the SystemVerilog interface construct can be used to create an interface for an asynchronous memory and memory controller.

The async_mem_bus is the name of the interface that will connect the asychronous memory (async_mem) and the memory controller (mem_ctrl). The memory controller just writes to the memory and reads back from it a few times before terminating.

SystemVerilog includes many improvements that remove the ambiguity with timescales found in Verilog. Instead of the `timescale operations, the timescale can be defined at the module level with the timeunit and timeprecision directives. Also useful is the ability to specify units when using the #(delay) syntax. The following snippet shows how these features may be used.

module system_verilog_time;
  timeunit 1ns;
  timeprecision 1ps;
 
initial begin
  #10ns    $display("%f", $realtime);
  #17ps    $display("%f", $realtime);
  #0.100ns $display("%f", $realtime);

The SystemVerilog task syntax is more elegant than the older Verilog style. In SystemVerilog, the inputs and outputs to the task can be defined within the task name declaration in parenthesis. This make it feel more similar to C. This snippets demonstrates some basic tasks for reading and writing a memory array. It also shows how these tasks may be used in a testbench.

module tbTasks;
 
bit clk;                       // clock signal.
logic [7:0] data_mem [0:255];  // array to simulate a memory.
int         ii,error_cnt;      // test variables.

The basic syntax for creating a class and creating an instance of the class is demonstrated in this snippet. An instance of the class is created using the new function. Optional values can be passed into the new function. Other functions and tasks can be created inside the class. This example shows a display function.

class TestClass;          // name of class.
 
int integer_a,integer_b;  // sample variables.
 
  function new(int a, int b); // function that is run when instance of object is created.
    integer_a = a;
    integer_b = b;
  endfunction

This snippet demonstrates a booth encoder implementation in Verilog. There is a state machine that controls the adding and shifting operations. The enable and done are the top level control and status signals. Included in the attached file is a test bench to exercise the module.

module booth #(parameter WIDTH=4) 
(
  input                    clk,
  input                    enable,
  input        [WIDTH-1:0] multiplier,                            
  input        [WIDTH-1:0] multiplicand,
  output reg               done,
  output reg [2*WIDTH-1:0] product
);

Verilog supports a limited number of compiler directive statements. One particular useful statement is the Verilog `ifdef. The syntax for the `ifdef is "`ifdef NAME". The ifdef should be paired with the `define directive which has the syntax "`define NAME VALUE". The `ifdef can be used in conjunction with the `else and must be closed with the `endif. Both of these directives are very similar to the C equivalent. The following example shows how a particular module may be conditionally instantiated.

`define USE_MODULE_A 
 
module verilog_if_def_example
(

The serial in parallel out shift register is another simple shift register, very similar to the serial in serial out shift register. The only difference being that entire contents of the shift register is the output. Please see Wikipeida for more discussion on the shift register and potential uses.

module serial_in_parallel_out #(parameter WIDTH=8) (
  input  clk,
  input  data_in,                     
  output [WIDTH-1:0] data_out

A serial in serial out is the simplest kind of shift register to create. The input is shifted in on the left side of the register and the data is shifted out the right side of the register. This snippet demonstrates a parameterized serial in serial out verilog shift register.

module serial_in_out #(parameter WIDTH=8) (
  input  clk,
  input  data_in,                     
  output data_out
                     );
 
// register to hold shift values.
reg [WIDTH-1:0] shift_reg;
 
// sync process.
always @(posedge clk)

This snippet demonstrates how to create a simple test bench in Verilog. The basic strategy is to create test bench module and instantiate the unit under test (UUT). After this, declare the inputs to the module as reg and the outputs as wires. Hook up the proper signals. Create a clock generation block and at least one signal stimulus block.

module verilog_tb;
 
reg  clk;              // clk signal.
reg  reset;            // reset signal.
reg  input_a, input_b; // input signals.
wire output_a;         // output signal.
 
// The unit under test.
test_module uut 
(