An accumulator can be used to keep a running tally of a value over time. This snippets demonstrates a simple accumulator in Verilog with a synchronous clear signal.

module accum #(parameter WIDTH=8) 
(
  input                  clk, clear,
  input      [WIDTH-1:0] d,
  output reg [WIDTH-1:0] q
);
 
always @(posedge clk)
  if (clear) q <= 0;
  else       q <= q + d;
 
endmodule

The CRC 16 CCITT is a very common and useful CRC algorithm. This snippets demonstrates how to implement this algorithm in VHDL. Also see the Verilog CRC16CCITT for additional discussion of this algorithm.

library ieee;
use ieee.std_logic_1164.all;
 
entity crc16ccitt is
  port ( clk       : in  std_logic;
         enable    : in  std_logic;
         reset_crc : in  std_logic;
         data      : in  std_logic;
         crc       : out std_logic_vector (15 downto 0)
         );
end crc16ccitt;

The CRC 16 CCITT is a common CRC implementation. This CRC algorithm is realized with a simple linear feeback shift register with exclusive taps inserted in 4 different stages in the CRC. A serial bitstream is shifted in and the 16 bit output CRC is valid at any time.

module crc16ccitt (
  input             clk, enable, reset_crc, data,
  output reg [15:0] crc
);
wire 		    xor12,xor5,xor0,xor16;
 
assign {xor16,xor0,xor5,xor12} = {crc[15]^data,xor16^1'b0,xor16^crc[4],xor16^crc[11]};
 
always @(posedge clk)
  if      (reset_crc) crc <= 16'hFFFF;

The generate statement in VHDL can be used to generate multiple instances of the same component. This is very similar to the Verilog Generate Statement. This example below shows the basic syntax of the generate statement and how it could be used to instantiate multiple flip flops.

library ieee;
use ieee.std_logic_1164.all;
 
entity generate_demo is
  port (
    clk      : in  std_logic;
    data_in  : in  std_logic_vector (7 downto 0);
    data_out : out std_logic_vector (7 downto 0)
    );

SystemVerilog introduced a new data type for a queue. The syntax for creating a queue is the same as for a dynamic array except that inside the brackets there is a $. The queue data type supports a number of functions such as queue.push_back(), queue.push_front(), queue.pop_front() and queue_.pop_back(). The names are self explanatory -- they simply push or pop items from the front or back of the queue. This snippet demonstrates how to push the contents of a file into a queue and how to read it back out and print it out while accessed like an array.

It is possible to combine file IO with dynamic arrays to load data from a file into a dynamically sized array. This snippet demonstrates how to open a file and read the contents into a dynamically sized array.

module systemverilog_dynamic_file_io;
int file,value,cnt=0,value_array[];            // dynamic array and variables.
initial begin
  file = $fopen("hexdata.dat","r");            // open file.
  while ($fscanf(file,"%x",value) != -1) begin // attempt to read a value from file.

Dynamic arrays in SystemVerilog allow for the creation of arrays during simulation runtime. It is no longer necessary to know the size of the array before the simulation starts executing. This snippet demonstrates how to create a dynamic array and how to add more elements to the array during runtime. The second array in the example also shows how it may be possible to inadvertently erase an entire array while attempting to allocate more items in the array.

module systemverilog_dynamic_array;
int test_array[];  // dynamic array syntax.
 
initial begin

The foreach construct in SystemVerilog provides a compact way of indexing through an array. The snippet below demonstrates the syntax of how to use foreach to go through both a 1 dimensional array and a 2 dimensional array.

module systemverilog_initialize_array_foreach;
 
int test_array[10] = '{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA};
int test_array_2d[3][10] = '{'{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA},
                             '{'h81,'h82,'h83,'h84,'h85,'h86,'h87,'h88,'h89,'h8A},

Array initialization in SystemVerilog has a syntax very similar to array initialization in C. The main difference is the usage of the quote (') character at the beginning of each row element of the array.

module systemverilog_initialize_array;
 
int test_array[10] = '{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA};
int ii,jj;
int test_array_2d[3][10] = '{'{'h1,'h2,'h3,'h4,'h5,'h6,'h7,'h8,'h9,'hA},
                             '{'h81,'h82,'h83,'h84,'h85,'h86,'h87,'h88,'h89,'h8A},

SystemVerilog introduced the built in support for constrained random variables. A variable can be made into a random variable by putting the "rand" keyword before the variable. Constraints can be applied to the variable by creating a constraint{} block and listing the constraints for the variable inside the block. This snippet demonstrates how to create a basic constrained random variable that represents a random pulse.

class RandPulse;
  rand int pulse_width;   // variables that can be randomized.
  rand int before_time;
  rand int after_time;