Verilog Pseudo Random Binary Sequence

Submitted by abettino on Fri, 06/04/2010 - 12:42

A pseudo random binary sequence (PRBS) generator can be a useful tool for generating a random sequence of numbers. Essentially a seed value is inputted into the module, the module is enabled, and every subsequent clock cycle a new pseudo random value is outputted. The feeback can be changed if a different polynomial value is desired.

module prbs (
 input            clk, enable,
 input      [7:0] seed,
 output reg [7:0] rand_num          
);
// generate feedback.
wire            feedback = rand_num[6] ^ rand_num[5] ^ rand_num[4];
// shift and load seed.
always @(posedge clk)
  if  (!enable) rand_num <= seed;
  else          rand_num <= {rand_num[6:0],feedback};
endmodule
 
module tb_prbs;
reg        clk,enable;
reg  [7:0] seed;
wire [7:0] rand_num;
// generate clock.
initial begin
  clk = 1'b0;
  forever #10 clk= ~clk;
end
// instantiate dut.
prbs dut (.clk     (clk     ),
          .enable  (enable  ),
          .seed    (seed    ),
          .rand_num(rand_num));
// apply stimulus. print out a few values.
initial begin
  enable = 0;
  seed = 'h12 ^ 'hCD;
  repeat (10) @(posedge clk);
  enable = 1;
  repeat (50) begin
    @(posedge clk);
    $display("%d",rand_num);
  end
  $stop;
end
 
endmodule

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LFSR

Submitted by Anonymous on Fri, 06/25/2010 - 22:41.

Look into LFSR's as well. The choice of feedback taps will result in different length sequences.

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Verilog Pseudo Random Binary Sequence

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