Verilog Simulators
Submitted by abettino on Thu, 01/19/2012 - 21:59There are many different verilog simulators. Some are free while some are very expensive. Some verilog simulators will support the libraries you are interested in simulating. Most likely you will be using whatever simulator the company you are working for wants to use. But if you feel like exploring other options here is a list of verilog simulators
Verilog And and Verilog And
Submitted by abettino on Thu, 01/12/2012 - 21:23Verilog has two different and operators. There is a bitwise and and a logical and. Using these operators in the wrong situations can cause undesired behavior. The bitwise verilog and operator will provide a bit vector that results from applying a bitwise and to each element in the source vectors. The logical verilog and operator will return 1 if both of the arguments are non zero. The following snippets demonstrates this behavior.
module verilog_and; reg [3:0] verilog_and_1; reg [3:0] verilog_and_2; reg [3:0] verilog_and_result; initial begin
System Verilog Mailbox with try_get
Submitted by abettino on Sat, 01/07/2012 - 09:48A mailbox in SystemVerilog is a very useful method of inter-process communication. Sometimes it is desired to read data from a mailbox from a process without blocking the process. This can be accomplished with the try_get() function as this snippet demonstrates. try_get() will return 0 if there is no data in the mailbox and 1 if there is data in the mailbox. It may also return -1 if there is an error condition.
program mailbox_test(); class Transmitter; // Transmitter sends values 0-19 mailbox #(byte) mb; function new(mailbox #(byte) mb);
BIT MULTIPLIER(8 BITS input)
Submitted by poiu_elab on Wed, 12/07/2011 - 06:37module bit_multiplier( input wire rst_n , input wire clk , input wire din_vld , input wire [7:0] multiplicand , input wire [7:0] multiplier , output reg [15:0] product , output reg dout_vld ); reg [3:0] counter; reg [7:0] reg_cand; reg [7:0] reg_er; reg [15:0] reg_product; reg din_vld1; reg din_vld2; reg m_enable; wire [15:0] reg_product_l = ~(counter > 0 & counter < 9) ? 16'b0 : reg_er[counter - 1] ? (reg_product[15:0] + {reg_cand, 8'b0}) : reg_product;
CARRY LOOKAHEAD ADDER
Submitted by poiu_elab on Wed, 12/07/2011 - 05:26module carry_lookahead_adder( input wire rst_n , input wire clk , input wire hrst , input wire w_in , input wire p_in , input wire [5:0] sum_p , input wire [3:0] din , output reg [5:0] sum ); wire [5:0] din_t; wire [5:0] g; wire [5:0] p; wire [5:1] ci; assign din_t = {2'b0,din}; assign g = { sum[5] & din_t[5], sum[4] & din_t[4], sum[3] & din_t[3], sum[2] & din_t[2], sum[1] & din_t[1], sum[0] & din_t[0] }; assign p = { sum[5] | din_t[5], sum[4] | din_t[4], sum[3] | din_t[3],
CARRY SAVE ADDER
Submitted by poiu_elab on Wed, 12/07/2011 - 03:45module carry_save_adder( input wire rst_n , input wire clk , input wire w_in , input wire p_in , input wire [7:0] sum_p , input wire [7:0] carry_p , input wire [3:0] din , output reg [7:0] sum , output reg [7:0] carry ); always @(posedge clk or negedge rst_n) begin if(~rst_n) begin sum <= 8'b0; carry <= 8'b0; end else if(p_in) begin sum <= sum_p; carry <= carry_p; end else if(w_in) begin sum <= sum ^ {4'b0, din} ^ {carry, 1'b0};
Barrel_Shifter
Submitted by poiu_elab on Wed, 12/07/2011 - 03:44module barrel_shifter( input wire rst_n , input wire clk , input wire data_in_vld , input wire left_or_right , input wire [3:0] num_bits , input wire [7:0] data_in , output reg data_out_vld , output reg [7:0] data_out ); parameter left = 1'b0; parameter right = 1'b1; always @(posedge clk or negedge rst_n) begin if(~rst_n) begin data_out <= 8'b0; data_out_vld <= 1'b0; end else if(data_in_vld) begin data_out_vld <= 1'b0; if(left_or_right == right)
Accumulator (under 10)
Submitted by poiu_elab on Wed, 12/07/2011 - 03:39module accumulator( input wire rst_n , input wire clk , input wire start , input wire [3:0] din //input <= 10 , output reg [9:0] dout , output reg dout_vld ); reg [7:0] k; always @(posedge clk or negedge rst_n or posedge start) begin if(~rst_n) begin dout <= 10'b0; dout_vld <= 1'b0; k <= 8'b0; end else if(start) begin dout <= 10'b0; dout_vld <= 1'b0; k <= 8'b0; end else if(k < 8'd99 ) begin dout <= din + dout; k <= k + 8'b1; end else if(k == 8'd99) begin dout_vld <= 1'b1;
Modulo (2^n) + 1 Adder -Edwin Jose
Submitted by arredwin on Wed, 03/16/2011 - 10:44module FA(u,y,a,b); input a,b; output y,u; or n1 (y,a,b); xnor n2(u,a,b); endmodule module FAF(u,y,a1,b1,a0,b0); input a1,b1,a0,b0; output y,u; wire x1,x2; or n3(x1,a1,b1); or n4(x2,a0,b0); xnor n5(u,a0,b0); nor n6(y,x1,x2); endmodule module squ(gi,pi,y,u); input y,u; output gi,pi; xor n7(pi,y,u); and n8(gi,y,u); endmodule module dia(si,pi,ci_1); input pi,ci_1; output si; xor n9(si,pi,ci_1); endmodule module bla(g,p,gi,pi,gi_1,pi_1); input gi,gi_1,pi,pi_1; output g,p; wire x3; and n10(p,pi,pi_1); and n11(x3,gi_1,pi);
Modulo (2^n) + 1 Adder -Edwin Jose
Submitted by arredwin on Wed, 03/16/2011 - 10:44module FA(u,y,a,b); input a,b; output y,u; or n1 (y,a,b); xnor n2(u,a,b); endmodule module FAF(u,y,a1,b1,a0,b0); input a1,b1,a0,b0; output y,u; wire x1,x2; or n3(x1,a1,b1); or n4(x2,a0,b0); xnor n5(u,a0,b0); nor n6(y,x1,x2); endmodule module squ(gi,pi,y,u); input y,u; output gi,pi; xor n7(pi,y,u); and n8(gi,y,u); endmodule module dia(si,pi,ci_1); input pi,ci_1; output si; xor n9(si,pi,ci_1); endmodule module bla(g,p,gi,pi,gi_1,pi_1); input gi,gi_1,pi,pi_1; output g,p; wire x3; and n10(p,pi,pi_1); and n11(x3,gi_1,pi);
