A pseudo random binary sequence (PRBS) generator can be a useful tool for generating a random sequence of numbers. Essentially a seed value is inputted into the module, the module is enabled, and every subsequent clock cycle a new pseudo random value is outputted. The feeback can be changed if a different polynomial value is desired.

module prbs (
 input            clk, enable,
 input      [7:0] seed,
 output reg [7:0] rand_num          
);
// generate feedback.
wire            feedback = rand_num[6] ^ rand_num[5] ^ rand_num[4];
// shift and load seed.

It is often desired to write data out to a file during a Verilog simulation. Fortunately, Verilog provides a simple way to do this. It is very similar to the way file writing is accomplished in C.

module verilog_write_file;
   integer file,ii;
   initial begin
      file = $fopen("test_output.dat");
      for (ii=0;ii<256;ii=ii+1) begin
         $fwrite(file,"%x\n",ii);
      end
      $stop;
   end
endmodule

The $monitor system task in Verilog can be used to display a state of a signal every time it changes. The following snippets demonstrates how the $monitor system task can be used to display the values of a and b as the simulation progresses.

module monitor_test;
 
reg [7:0] a, b;
 
initial begin
  $monitor("a=%d b=%d",a,b);
  #10 a = 0;
  b = 4;
  #100 a = 22;
  #100 b = 100;
  #100 a = 35;
  #100 b = 0;
  #10 $stop;
end
 
endmodule

The $readmemb system task in Verilog allows a program to read data from a text file with binary formatted data. For example, if a file test_data_bin.dat contains the data.

00000001000000010000000100000001
11111111111111111111111111111111
01010101010101010101010101010101
00000000000000000000000000000000
10101010101010101010101010101010
01010111110101111110101111101111
11111111111111111111111111111111
10101010101010101010101010101010

Then this snippet can read in this data and display it.

module verilog_readmemb;

The $readmemh system task in Verilog allows a program to read data from a text file with hexadecimal formatted data. For example, if a file test_data.dat contains the data.

00000001
ffffffff
abcd1234
55558888
00000001
ffffffff
abcd1234
55558888

Then this snippet can read in this data and display it.

module verilog_readmemh;
reg [31:0]  data_ram [0:7];   // array to store the data in.
integer     ii;               // loop variable.
initial begin

The always block in verilog can be used to model either combinational or sequential logic. It starts with the always keyword and then the sensitivity list. After that is the begin and end along with an optional block label.

 
always @(posedge clk or negedge n_reset)
  begin : FLIP_FLOP
    if (!n_reset) begin
      q <= 1'b0;
    end
    else begin
      q <= d;
    end
  end

The carry look ahead adder is similar to the Ripple Carry Adder, but it can operate faster due to the way that the carry logic is generated. For more information about the algorithm, see the Wikipedia page. This snippet is a parametrizable implementation of the carry look ahead adder.

module cla #(parameter WIDTH=4)
(
   input      [WIDTH-1:0] a,b
   output reg [WIDTH:0]   sum
);
reg [WIDTH:0]             carry;

Mailboxes are a way in SystemVerilog to provide inter-process communication. They essentially act like a FIFO where one process can write to the mailbox and the other process can read from the mailbox. This snippet demonstrates how to create a transmitter and receiver that will read and write to mailboxes. Writing to the mailbox is accomplished with the put() function and reading is accomplished with the get() function.

program mailbox_test();
 
class Transmitter;   // Transmitter sends values 0-19
mailbox mb;
 
  function new(mailbox mb);
    this.mb = mb;

The Verilog for loop is very similar to the for loop in C. The block is created with the begin and end keywords just like other blocks in Verilog. Notice that the ++ operator is not supported for incrementing variables in Verilog 2001, but it is supported in SystemVerilog.

module verilog_for;
integer ii;
initial begin
  for(ii=0;ii<10;ii=ii+1) begin
    $display("ii=%d",ii);
  end
  $stop;
end
endmodule;

The task in Verilog provides a convenient mechanism for encapsulating a chunk of code that will be executed multiple times. The most useful place for a task is in a testbench. The following snippets demonstrates the syntax for the task in verilog. Notice that first comes the task name followed by the inputs and outputs for the task. The initial block shows how the task can be called.

module verilog_task;
 
task add;
input [7:0] a;
input [7:0] b;
output [7:0] c;
  begin
    c = a + b;
  end
endtask
 
integer value1, value2,value3;
 
initial begin